Due to advancements in processing technology, complex integrated circuits (ICs) can be designed using various levels of abstraction. Using a hardware description language (HDL), circuits can be designed at the gate level, the register transfer level (RTL), and higher logical levels. When designing using an HDL, the design is often structured in a modular manner. The designer describes a module in terms of the behavior of a system, the behavior describing the generation and propagation of signals through combinatorial modules from one set of registers to another set of registers. HDLs provide a rich set of constructs to describe the functionality of a module. Modules may be combined and augmented to form even higher level modules.
To reduce design costs, designers often incorporate previously created designs that have been provided either from within an enterprise or from a commercial provider. Libraries of pre-developed blocks of logic have been developed that can be selected and included in a circuit design. Such library modules include, for example, adders, multipliers, filters, and other arithmetic and digital signal processing (DSP) functions from which system designs can be readily constructed. The engineering community sometimes refers to these previously created designs as “IP cores” (intellectual property cores), or “logic cores,” and such terms may be used interchangeably herein. The use of pre-developed logic cores permits faster design cycles by eliminating the redesign of circuits. Thus, using cores from a library may reduce design costs.
Prior to implementation, an HDL design can be simulated to determine whether the design will function as required. Wasted manufacturing costs due to faulty design may thereby be avoided. Numerous tools are available for simulating circuit designs including, for example, high-level modeling systems (HLMS) and HDL simulators.
Due to object-oriented reuse of design code, an HDL design often contains modules written in different HDLs. Two commonly used HDLs are VHDL (VHSIC (Very High Speed Integrated Circuits) hardware description language) and Verilog. HDL specifications that utilize two or more HDLs may be referred to as mixed-language designs. A module defined in one language can include another module of either language as a sub-module, with no restriction on either the depth of the instantiation hierarchy or the number of times the design hierarchy switches language type. Signals used as ports in module instantiations can pass language boundaries as well, with no restrictions other than those imposed by the design. For ease of explanation, examples and embodiments are primarily described using a mixed-language where each module of the design is described with either the Verilog or the VHDL language. As used herein, VHDL components and Verilog modules are referred to generically as modules.
Mixed-language designs can be difficult to simulate efficiently, due to the differing formats and capabilities of the different HDLs. One solution for mixed-language simulation performs code generation (i.e., executable/assembly/object code generation from HDL for effecting compiled code simulation) on a per module basis. During code generation, a distinctive representation is generated for each of the Verilog and VHDL modules instantiated. These module-based representations are read in at run time and used to effect the simulation. In such models, the port connections to convert and propagate signals between the Verilog and VHDL modules are configured during simulation runtime, often creating new signals that may increase simulation workload. To handle data type conversion and complex port connections necessary to propagate signals across language boundaries, additional implicit HDL processes may be needed to map and convert signals appropriately. The combined effect of handling signal propagation and additional HDL processes increases simulation complexity and memory requirements, and reduces simulation runtime efficiency.